1. Field
Exemplary embodiments of the present invention relate generally to a memory system and, more particularly, to a memory system performing encoding and decoding operations and an operation method thereof.
2. Description of the Related Art
Recently, for further increasing memory integration, memory systems (data storage devices), such as solid state drives (SSD), have started to employ a multi-level cell (MLC) based memory capable of storing two or more bits in a single memory cell.
However, as the number of bits programmable into a single memory cell increases, the error rate of a memory during a read operation may worsen due to interference between the multiple levels. The error rate may become rather substantial as program and read operations are repeated, thereby reducing the overall reliability of the memory system. To solve this problem, memory systems employ an error correction code.
Heretofore, well-known error correction codes include a hamming code, a Reed-Solomon code, a Bose-Chaudhuri-Hocquenghem (BCH) code, and a block-wise concatenated BCH (BC-BCH) code comprising the BCH code as a constituent code. The BC-BCH code is a strong error correction code, having a high code rate and a low error rate. However, the BC-BCH code has a deficiency in that the error floor occurs in a high signal to noise ratio (SNR). In general, a (1, 1) error pattern representing failure of a single row parity and a single column parity has a substantial influence on the error floor. That is, as the size of a block becomes greater, the probability of increasing the number of error patterns increases and thus the probability of the error floor also increases in the block. Downsizing of the block may be a solution for the problem, however, downsizing of the block may require increasing the number of the constituent codes, which cause lowered error rate.